A System On Chip (SOC) includes a semiconductor memory device (e.g., on-chip memory or the like). Usually 10% to 40% of an area of the SOC is occupied by the on-chip memory. The on-chip memory can be a Static Random-Access Memory (SRAM), a Read-Only Memory (ROM), and a register file. The on-chip memory contains two types of hardware circuits (e.g., bitcell array circuit and periphery circuit). The bitcell array circuit includes an array of bitcells. Each bitcell stores 1-bit of data. The periphery circuit includes logic gates to control a read operation and a write operation.
A hold margin of the on-chip-memory indicates a delay between an internal clock signal and a data signal (e.g., address signal, enable signal, or the like). The hold margin corresponds to a data path delay (D2) greater than an internal clock path delay (D1) as shown in FIG. 1. Conventionally the data signal is delayed to meet a hold margin. FIG. 1 shows implementation of the delay using logic gates in the data path. A circuit 100 includes a clock generator 102, a set of delay logics 104a-104c, a logic 106, a latch clock generator 108, a latch 110, a decoder 112, a set of input/output (IO) circuits 114a-114c. The latch clock generator 108 is connected to the latch 110, where the latch 110 is connected to the decoder 112. The clock generator 102, the set of delay logics 104a-104c, the logic 106, and the latch clock generator 108 are included in a control block 150.
Since the logic gate delay varies across Process, Voltage and Temperature (PVT) corners, the number of delay logics 104a-104c required are very high to satisfy the hold margin across the PVT range. This results in limiting performance of a compiler associated with the SOC. Further, the number of delay logics 104a-104c placed is based on the biggest instance, so small instances will unnecessarily contain an extra delay, which hampers performance of the semiconductor memory device.
Further, the required amount of delay to meet the hold margin is different for different sizes of the semiconductor memory device. Further, the same number of delay logics 104a-104c is placed inside the control block 150, regardless of the different sizes of the semiconductor memory device. Thus, the number of delay cells cannot be changed based on the size of the semiconductor memory device and the delay required for biggest instance (i.e., large numbers of usage of the 10 circuit) is used in smaller instances (i.e., less numbers of usage of the 10 circuit) as well. This hampers performance of the smaller instances.